Return to BSD News archive
Received: by minnie.vk1xwt.ampr.org with NNTP id AA145 ; Thu, 28 Jan 93 21:02:17 EST Xref: sserve comp.unix.bsd:10500 comp.sys.ibm.pc.hardware:42482 Path: sserve!manuel.anu.edu.au!munnari.oz.au!spool.mu.edu!yale.edu!qt.cs.utexas.edu!cs.utexas.edu!sun-barr!news2me.EBay.Sun.COM!exodus.Eng.Sun.COM!sun!amdcad!dvorak.amd.com!tdbear From: tdbear@dvorak.amd.com (Thomas D. Barrett) Newsgroups: comp.unix.bsd,comp.sys.ibm.pc.hardware Subject: Re: Vesa Local Bus and Companies (please read) Message-ID: <1993Jan27.191330.4938@dvorak.amd.com> Date: 27 Jan 93 19:13:30 GMT References: <1993Jan26.220906.26671@netcom.com> <1993Jan27.044856.15406@wam.umd.edu> <1993Jan27.050642.15880@wam.umd.edu> Organization: Advanced Micro Devices, Inc.; Austin, Texas Lines: 36 In article <1993Jan27.050642.15880@wam.umd.edu> tictac@wam.umd.edu (Shake it to the Left) writes: >Then WHY does [deleted] sell 486/DX50's claming to have >3 VLB slots in them? Although they may have a true 50MHz CPU, they might operate the rest of the system at 25MHz. You will have to ask them what the clock rate is on the vl-bus. The rules are that only certified VL-Bus systems have a special VESA VL-Bus compliance label. The compliance testing requirements are just being finalized and will soon be off to the mags and the various compliance labs. If a company is not on the committee, then they will most likely have to be certified by an independent lab. Those on the committee *might* be permitted to self-certify. Only 33MHz and less systems can have 3 physical slots. Right off the bat these are in violation UNLESS they are buffered (probably not). I was amazed that some companies are offering so-called VL-Bus compatible machines with well over 200pF of UNLOADED capacitance on the Bus. These companies generally just take a chip vendor's demo platform and stamp out massive units. Unfortunately, these demo platforms typically do not conform to any intelligent design parameters. One that I looked at recently (the over 200pF one) had the two banks of SRAM, the 8 SIMM modules, and the 3 local bus slots all on the motherboard. The SRAM and DRAM alone put the recommeded bus capacitance at the limit. Naturally, adding buffers to the DRAM would have required an extra waitstate or faster DRAM. But, if I had such a system that would be a whole lots better than having parity errors (assuming you have parity). -- |Tom Barrett (TDBear), Sr. Engineer|tom.barrett@amd.com|v:512-462-6856 | |AMD PCD MS-520 | 5900 E. Ben White|Austin, TX 78741 |f:512-462-5155 | |"No is yes, And we're all free" ---Tracy Chapman, "Why?" | |My views are my own and may not be the same as the company of origin |