*BSD News Article 10910


Return to BSD News archive

Received: by minnie.vk1xwt.ampr.org with NNTP
	id AA911 ; Tue, 09 Feb 93 17:38:06 EST
Path: sserve!manuel.anu.edu.au!munnari.oz.au!spool.mu.edu!howland.reston.ans.net!usc!isi.edu!gremlin!lazarus.nrtc.northrop.com!dec
From: dec@lazarus.nrtc.northrop.com (Dwight E. Cass)
Newsgroups: comp.unix.bsd
Subject: [386BSD] Are your 16550 "compatable" com ports hanging?
Message-ID: <44533@gremlin.nrtc.northrop.com>
Date: 8 Feb 93 03:42:05 GMT
Sender: news@gremlin.nrtc.northrop.com
Followup-To: dec@nrtc.northrop.com
Organization: Northrop Research & Technology Center, Palos Verdes, CA
Lines: 65
Summary: Fix for STB DSP/550 16550 compatable com ports

I recently bought what I thought was a 16550 board from STB Systems,
Inc. called the DSP/550.  Supposedly it has two 16550 ports and a 
parallel port.  Well, when I built a kernel with FIFO support (using
every com driver I could find, from cgd original fix, through patch
0.1 and 0.2, and finally cgd's latest goodies..), the system would
boot up just fine the first time as a hardware reset.  However, the
second time, the system would hang as it finished execution of
/etc/rc.

I called STB Systems and found out that I don't have a 16550, but
instead have a ST16C552 from Startech (not to be confused with
Startech Semiconductors).  Yes, this chip looks and feels like a
16550 - but it has one little side-effect.  Whenever you reset the
FIFO after it has been on, you will get a FIFO error as the receive
shift register empties out (don't ask me why, other than I can show
you in the documentation where it warns you that FIFO reset will
not clear the receive shift register, and I have had code in the
kernel to capture the sequence...).  So, enclosed is a small
patch (based loosely on cgd latest com driver - but you should be
able to insert it into any of the com drivers hanging around), which
solved my problem.  Basically, after doing a FIFO reset - we do
a DELAY(100) to let things settle then clear the pending interupts
by reading the line status register.  Note - at least on my system,
the DELAY(100) in both cases are ABSOLUTELY REQUIRED.

----- Begin cut here

*** ./com.c.old	Sun Feb  7 19:19:20 1993
--- ./com.c	Sun Feb  7 19:19:28 1993
***************
*** 206,211 ****
--- 213,222 ----
  	outb(com+com_fifo,
  		FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER);
  	DELAY(100);
+ 	(void) inb(com+com_lsr);	/* Clr the FIFO/framing error
+ 					 * caused by the FIFO_RCV_RST
+ 					 * on a ST16C552 */
+ 
  	if (inb(com+com_iir) & IIR_FIFO_MASK) {
  		com_fifosize[unit] = 15; /* has fifo... */
  		printf(" fifo enabled", unit);
***************
*** 1000,1005 ****
--- 1011,1020 ----
  	outb(com+com_ier, IER_ERXRDY|IER_ETXRDY|IER_ERLS|IER_EMSC);
  #ifndef COM_IGNOREFIFO
  	outb(com+com_fifo, FIFO_TRIGGER|FIFO_RCV_RST|FIFO_XMT_RST);
+ 	DELAY(100);			/* Let the FIFO settle */
+ 	(void) inb(com+com_lsr);	/* Clr the FIFO/framing error
+ 					 * caused by the FIFO_RCV_RST
+ 					 * on a ST16C552 */
  #endif /* COM_IGNOREFIFO */
  	(void) inb(com+com_iir);
  	com_mstat[unit] = inb(com+com_msr);

----- End cut here

Hopes this helps others with similar hanging problems,
/dec

Dwight E. Cass                 dec@nrtc.northrop.com | Rocky, watch me
Automation Sciences Laboratory, Northrop Corporation |   pull a rabbit out
One Research Park, Palos Verdes Peninsula, CA  90274 | of my hat...
(310) 544-5393                  Home: (310) 473-1703 |   -- Again?