Return to BSD News archive
Path: sserve!manuel.anu.edu.au!munnari.oz.au!news.Hawaii.Edu!ames!agate!doc.ic.ac.uk!uknet!cf-cm!myrddin.isl.cf.ac.uk!paul
From: paul@isl.cf.ac.uk (Paul)
Newsgroups: comp.os.386bsd.questions
Subject: sigseg and sigbus errors and cache problems
Message-ID: <1993Feb24.144055.13545@cm.cf.ac.uk>
Date: 24 Feb 93 14:40:54 GMT
References: <1993Feb17.193715.3658@spang.Camosun.BC.CA>
Sender: news@cm.cf.ac.uk (Network News System)
Organization: Intelligent Systems Lab, ELSYM, Universiity of Wales, College of
Cardiff.
Lines: 20
I've been having lots of traps when doing long compiles and I noticed a
few articles recently that suggest that it's because of cache problems.
I haven't disabled my cache yet, I'm going to try that today but I
have opened up my box and checked out the specs. The manual states that
there should be 25ns data cache and 20ns tag cache. I've actually got
20ns tag AND data cache. All my BIOS settings seem OK, I can't see why
faster than necessary cache would cause problems but does someone know
any better.
While I'm at it, could someone post a brief synopsis of what the
different caching mechanisms are, write-back/through etc.
Thanks.
--
Paul Richards, University of Wales, College Cardiff
JANET:paul@uk.ac.cf.isl Internet:paul@isl.cf.ac.uk
UUCP: paul@cf-isl.UUCP or ...!uunet!mcsun!uknet!cf!isl!paul