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From: juengst@saph2.physik.uni-bonn.de (Henry G. Juengst)
Subject: Re: QIC NEWS; vol. 1, no. 3
Message-ID: <1993Mar23.175701.21077@olymp.informatik.uni-bonn.de>
Lines: 39
Sender: usenet@olymp.informatik.uni-bonn.de
Reply-To: juengst@saph2.physik.uni-bonn.de
Organization: Universit"at Bonn, Informatikinstitut, R"omerstr 154, W-5300 Bonn 1
References: <1993Mar19.114125.9051@netcom.com>
Date: Tue, 23 Mar 1993 17:57:01 GMT
In article <1993Mar19.114125.9051@netcom.com>, jmonroy@netcom.com (Jesus Monroy Jr) writes:
[...]
> This code clip shows the right way and wrong way.
>
> ;; wrong way
> outw dx, ax ;; write a word (16-bits) to a port
>
> ;; right way
> outb dx, al ;; write the LSB (least significant byte)
> xchg al,ah ;; exchange high for low
> nop ;; wait settle time (about 2 clock cycles)
Are you sure your "right way" will work on the next generation of 80x86 ?
May be there will be CPUs with 200 MHz clock frequency (not a vision, it's
real, but not in the PC world, yet) and parallel processing available later.
The past shows that every code with fixed encoded delays fails anywhere.
Of course that's not your failure, it's the stupid PC hardware design. :-(
But it's your problem ... :-)
> outb dx, al ;; write new LSB
[...]
> ___________________________________________________________________________
> Jesus Monroy Jr jmonroy@netcom.com
> /386BSD/device-drivers /fd /qic /clock /documentation
> ___________________________________________________________________________
Henry
--
juengst@boss1.physik.uni-bonn.de [131.220.221.30] {u}
juengst@saph2.physik.uni-bonn.de [131.220.221.12] {d}
juengst@pib1.physik.uni-bonn.de [131.220.221.2] {s}
I'm only speaking for myself, but not for anybody else !