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Xref: sserve comp.unix.internals:5993 comp.unix.programmer:10407 comp.unix.bsd:12229 Newsgroups: comp.unix.internals,comp.sun.sys.hardware,comp.unix.programmer,comp.unix.bsd Path: sserve!newshost.anu.edu.au!munnari.oz.au!news.Hawaii.Edu!ames!agate!howland.reston.ans.net!math.ohio-state.edu!cs.utexas.edu!news.uta.edu!cse.uta.edu!vrao From: vrao@cse.uta.edu (Vinay Rao) Subject: mbvar structures and kernel details of BSD Unix Message-ID: <1993Jul9.075003.6663@news.uta.edu> Sender: news@news.uta.edu (USENET News System) Nntp-Posting-Host: cse.uta.edu Organization: Computer Science Engineering at the University of Texas at Arlington Date: Fri, 9 Jul 1993 07:50:03 GMT Lines: 0 #! rnews 2083 sserve.cc.adfa.oz.au Xref: sserve comp.unix.internals:5994 comp.unix.programmer:10408 comp.unix.bsd:12230 comp.sys.sun.hardware:9185 Newsgroups: comp.unix.internals,comp.unix.programmer,comp.unix.bsd,comp.sys.sun.hardware Path: sserve!newshost.anu.edu.au!munnari.oz.au!news.Hawaii.Edu!ames!elroy.jpl.nasa.gov!swrinde!cs.utexas.edu!news.uta.edu!cse.uta.edu!vrao From: vrao@cse.uta.edu (Vinay Rao) Subject: mbvar structures and kernel internals of BSD Unix Message-ID: <1993Jul9.075202.6787@news.uta.edu> Sender: news@news.uta.edu (USENET News System) Nntp-Posting-Host: cse.uta.edu Organization: Computer Science Engineering at the University of Texas at Arlington Date: Fri, 9 Jul 1993 07:52:02 GMT Lines: 35 Newsgroups: comp.unix.internals,comp.sys.sun.hardware,comp.unix.bsd, comp.unix.programmer Subject: mbvar structures in BSD kernels Summary: Followup-To: Distribution: world Organization: Computer Science Engineering at the University of Texas at Arlington Keywords: Hi Netters, I wanted to know what is the exact purpose of mbvar structures . Does the driver routines as found in the bdevsw & cdevsw structures call these ? The Sun device driver manuals seem to say that mbvar has some elaborate data structures for each of the cards with probe routines (used by autoconfiguration) go,stop routines for DMA the addresses at which the cards internal chip registers ( control & status etc) can be accessed. Does this mean that there are general stop & go kernel routines for DMA which any drivers can call while setting up DVMA giving the device specific addresses & memory sizes? It also says that if DVMA space is not adequate then the controller's mbdevice structures are put in await queue. I am not able to visualise how this can happen and what are the trace of the sequence of events that start from the device switch table that go upto the harware details of the bus structures & routines. Is there a bus driver which is being called ? If any of you ( especially those at Sun ) know about these please let me know. Thanks in advance Vinay Rao (vrao@csr.uta.edu)