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Path: sserve!cserve.cs.adfa.oz.au!wkt
From: wkt@cserve.cs.adfa.oz.au (Warren Toomey)
Subject: Re: Food for thought
Message-ID: <1993Aug16.011212.9111@sserve.cc.adfa.oz.au>
Keywords: logic permutations combinations factorials
Sender: news@sserve.cc.adfa.oz.au
Organization: Australian Defence Force Academy
References: <jmonroyCBssIJ.3rp@netcom.com>
Date: Mon, 16 Aug 1993 01:12:12 GMT
In article <jmonroyCBssIJ.3rp@netcom.com>, jmonroy@netcom.com (Jesus Monroy Jr) writes:
|> Some Formal Logic... try it!
|> ----------------------------
Please send all followups to sci.math.symbolic.
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Warren Toomey wkt@csadfa.cs.adfa.oz.au
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From: joe@jshark.inet-uk.co.uk (Joe Sharkey)
Subject: Re: More annoyance on the DMA problem
Organization: Individual Network (UK)
Date: Sun, 15 Aug 1993 22:59:44 GMT
Message-ID: <CBtp7L.FpM@jshark.inet-uk.co.uk>
References: <adlerCBpvpJ.K5v@netcom.com> <jmonroyCBqEIt.Hq4@netcom.com>
Lines: 76
Hmm, I think I've worked out J.Monroy's DMA problem - some of them anyway ;)
In article <jmonroyCBqEIt.Hq4@netcom.com> jmonroy@netcom.com (Jesus Monroy Jr) writes:
> MR. ALDER this is the last time I will answer you on-line.
> If you insist that I am incorrect, then send me the evidence
> or send me your theories. I have been wrong in the past and
> I am not beyond making my errors public, in case you haven't
> noticed.
Jesus, you're wrong. Repeating over and over that you aren't won't change
anything.
>>> On a 4MHz PC, a refresh takes 5 clock cycles.
>>>
> Where did you get this number?
> What is your source?
> What took you so long to find it?
Something like the IBM PC/XT Tech Ref? From memory, it's Ch 1 - System
Specification, about page 5.
But you didn't have this last time I mentioned it.
>>> Which means the
>>> DMA request will be delayed at most 1.25 microseconds. Of course,
>>> all real PCs are faster than 4MHz, but let's assume 4MHz to prove
>>> my point. The 1.25 microsecs is substantially less than the 13
>
> Programming a DMA controller is not done in sub-microseconds,
> consider that.
True, but not interesting. One programs the DMA controller *before* the
transfer starts.
I suspect you're trying to use the DMA chips in one of two way -
both obviously silly:
a) Program the FDC to start the transfer, then set up DMA chip
or
b) Set up DMA chip, then start the FDC. Only trying 1 byte/DMA.
This *would* fast DMA programming.
Another message implies you want to add context-switch time into your
equation, which implies you're lacking insight in how hardware works.
> If you insist on proving your incompetance on-line that
> is your business, but I can not support you.
Be nice to idiots - they may your next pay cheque ;)
> My numbers are all verifiable, consider this in your
> next statement.
`Verifiable', but wrong.
> If you have some helpful suggestions, some keen insight,
> a clarviant perception, or even a minor mathematical
> experience, then please by all means post.
> IF NOT, e-mail me and let clear this up.
> Don't waste the Nets time with your ranting.
Hey, Jesus! The bit above is great - you ought to read it!
> Thank your for your attention.
``Have a nice day''
>Jesus Monroy Jr
joe.
--
Joe Sharkey joe@jshark.inet-uk.co.uk ...!uunet!ibmpcug!jshark!joe
150 Hatfield Rd, St Albans, Herts AL1 4JA, UK Got a real domain name
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