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From: adler@netcom.com (Bruce Adler)
Subject: Re: More on the DMA timing problem
Message-ID: <adlerCBy8o4.I9v@netcom.com>
Organization: Netcom Online Communications Services (408-241-9760 login: guest)
References: <jmonroyCBKrE9.76n@netcom.com> <jmonroyCBopts.KM8@netcom.com> <1993Aug16.072355.292@ica.philips.nl>
Date: Wed, 18 Aug 1993 09:50:28 GMT
Lines: 27
In article <1993Aug16.072355.292@ica.philips.nl> adrie@ica.philips.nl (Adrie Koolen) writes:
>When using 8 bits wide DMA in Single Transfer mode, each DMA transfer
>takes about 3 ms. 64 KB then takes 192 ms, which certainly is longer
^^^^ ^^^^^^
>than the refresh period, although most DRAMs will operate with refresh
>periods of 192 ms (though not guaranteed!).
I assume in first instance you meant "ms" to be microseconds and in
the second instance it means milliseconds. Regardless, your timing
numbers are way to high and conflict with your later estimate of
a max thruput of 5 MB/s.
>When using Demand Transfer mode and 16 bits wide DMA, transfer speed
>maxes out at some 5 MB/s, so 64 KB would take some 13 ms. This is still
^^^^^^
>longer than the refresh period (4 or 8 ms, I believe).
I always assume that a DMA /transfer takes four or five cycles (depending
whether it's a zero wait state device and/or how quickly your memory
controller recognizes the DMA request from the device). Therefore, on
a 10MHz bus that's about 500 nsecs per transfer, not 3 usecs. And 64KB
would take atleast 35 milliseconds, but since the CPU gets to use the
bus inbetween each byte transfer figure 70 to 100 msecs typically.
My guess is that a 10MHz bus probably maxes out at 1 to 1.5 million
transfers per second and might go as high as 2 to 2.5 million transfers
per second if you put the CPU to sleep.