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From: jmonroy@netcom.com (Jesus Monroy Jr)
Subject: A review of the Intel 82077/82078 - a floppy drive controller
Message-ID: <jmonroyCD32Fp.7zE@netcom.com>
Keywords: FDC NEC765 Intel8272 Intel 82077/78 review FIFO DMA
Organization: NETCOM On-line Communication Services (408 241-9760 guest)
Date: Thu, 9 Sep 1993 10:57:24 GMT
Lines: 177
Released
A review of the Intel 82077/82078
------------------------------------------
(CHMOS Single-chip Floppy Disk Controller)
------------------------------------------
CAUTION CAUTION CAUTION
-------------------------
Don't write to tell me this doesn't belong in your
newsgroup. All the Newsgroups I post-to have a person that
I am coordinating with for new QIC/FDC drivers. These
newsgroups were started by ARPA (formerly DARPA) for R&D
(Research and Development), which is what I am doing.
Also this information is of a highly technical nature
and may not apply to your life (problems). So feel free
to hit the "n" button now or put my name in your "kill file".
If you want to know how the kill file works, write to:
jemenaker@nike.calpoly.edu
or
garrett@sba70.berkeley.edu
or
jcburt@gastibm.larc.nasa.gov
Before you fire off another message to me entitled:
"You moron, 'Please do not cross-post... la-de-da'". This
review applies to all designers/implementors of the QIC/FDC
on the IBM PC AT with these variations:
FDC COMPATIBLE WITH: Intel 8272, NEC 765A/B
BUS: ISA/EISA/Microchannel/VESA Local/Intel Local
DATA TRANSFER SPEEDS: 250/300/500/1000/2000 Kbits/sec
IBM MODEL: PC-XT, PC AT, PS/2, PS/2 model 30
DEVICES INVOLVED: The Standard Floppy drives,
FDC based QIC tape drives,
the 2.88 MB and 4 MB floppy drives.
BENIFITS TO: LAPTOP and systems with large bus latency.
NEW Incredible features - yeah right :)
---------------------------------------
Reset - defaults the chip to a standard i8272.
A 16 Byte FIFO with system lock (neato).
A new Perpendicular Recording Mode (supposed to be better).
Register compatiblity with the PS/2 (more on this later).
Tape Drive Select Register (WOW!).
Requires a 24MHz Crystal.
MEANINGLESS DRIVEL
------------------
From: DILBERT by Scott Adams
--------------------------------------------------------------
"-Government Statistics show that office productivity went
*down* as computers became widely used.
-But I didn't believe it.
-So I wrote a little software program to test that conclusion.
-It only took a month, but it produce some impressive data.
-In fact, it was so impressive it took a week to figure out how
to print it.
-But before I could print, my computer crashed and I didn't
have backup copies.
-So, it seems the government was right; Computers are to
blame for the decline in productivity.
====Do you think the employees could be partly responsible?
-Sure, find a scapegoat."
--------------------------------------------------------------
THE REVIEW
----------
The question remains: What about the DMA problem?
My first line of thought is that the net has labored enough
on this issue for now. Help on this has come from the most
unlikely sources. This all gladifies me. I am, to some extent
overwhelmed at the trouble people are taking to corner
me on my stupid mistakes. :) (Yipeee,,, this was non-sense.)
OK, as to the question: I have several good ideas from
people and they will be passed to the beta group for testing.
Results will be posted when they are available.
Beneifits
---------
The reset - with a default to the "standard" Intel 8272a
gives us assurance to some backwards compatibility. An
incredible amount of configuration is now available to the FDC
including "software reset", protected settings, version
checking, relative seeks, power down modes and more. However,
some problems may arise with the new DMA timing (see comments
below).
The 16 Byte FIFO is meant to beneift applications with
the newer bus types (Microchannel, EISA, LOCAL). The appliable
system lock protects the FIFO from being canceled durning a soft
reset. Hence, the FIFO lock is meant for power-up-time
settings by implementors.
I have never heard of, till this date, a Perpendicular
Recording Mode. So, maybe someone in the hardware section can
thread and let us know what this is about.
The new register compatiblity with the PS/2 makes it
possible for the QIC-40/80 implementations to work without the
strict timing requirement support from the OS. Also, the
DMA problem will be negated with the new FIFO. For us
QIC-40/80 people this is a great plus. What this means for me
is - just as the serial port people recommend the NS 16550;
I now recommend the Intel 87078 as a FDC, with qualificaitons.
The qualification is that I haven't seen this new chip so when
I do, I may give it more support.
A new Tape Drive Select Register needs to be qualified.
So I will check with the QIC-40/80 manufactures that I have on
my list.
The new requirement for a 24MHz Crystal will make
allowances for drives/diskettes with more capacity. The
aforementioned 2 and 4 meg drives should be a seamless
implementation.
This completes my notes/comments on this subject.
Comments, discussions, retorts, critiziums, flames, roasting,
Toaster wars are welcome.
Please leave the social remarks to a minimum (I.E., "< 10%").
NOTES on the DMA timing chart
-----------------------------
legend
======
DRQ DMA Request signal
DAK DMA Acknowledge signal
__ __
RD/WR READ or WRITE (driven low)
__ __
The new timing for DRQ to RD/WR is 6us. This is with
__ __
threshold = 1. The DRQ now can stay HI through DAK and RD/WR.
__ __
(YES, I said the DAK and RD/WR can be initated simultaeously.)
__ __
Formerly RD/WR timing was tied to the DRQ timing (ending of
__ __
the RW/WR was based on DRQ initiate). Also new the DAK may
__ __
not invert (or revert) the signal until the RW/WR is complete.
Formerly, the DAK signal-relation was not well defined (or in
the National Semiconductor case it had a set (time) length).
___________________________________________________________________________
Jesus Monroy Jr jmonroy@netcom.com
Zebra Research
/386BSD/device-drivers /fd /qic /clock /documentation
___________________________________________________________________________