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Path: sserve!newshost.anu.edu.au!munnari.oz.au!news.Hawaii.Edu!ames!cronkite.cisco.com!cisco.com!vandys From: vandys@cisco.com (Andrew Valencia) Newsgroups: comp.os.386bsd.questions Subject: Re: The reason for stray interrupts Date: 27 Oct 93 18:10:53 GMT Organization: cisco Systems Lines: 16 Message-ID: <vandys.751745453@cisco.com> References: <2ais9gINN2t8@xs4all.hacktic.nl> <2alpnh$1cm@werple.apana.org.au> NNTP-Posting-Host: glare.cisco.com >ptuomola@hacktic.nl (Petri Tuomola) writes: >>Many people have been asking why their machines display "ISA strayintr 7" >>messages. This is an extract from /sys/arch/i386/isa/isa.c: Sigh. I seem to post this every month or so. The problem is the way interrupts are cleared from the two chained PIC's. If you disable the chained IRQ to the second PIC, or if you use auto-EIO mode, or if you use selective EOI to finish a pending interrupt, it doesn't happen. The simplistic code which shotguns the two PICs in a row unconditionally is at fault. Andy