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From: j@uriah.sax.de (J Wunsch)
Newsgroups: comp.os.386bsd.development
Subject: Re: [FreeBSD 1.0R] DMA Problems?
Date: 15 Dec 1993 17:07:57 +0100
Organization: Private U**X site; member IN e.V.
Lines: 33
Message-ID: <2encotINN3sq@bonnie.sax.de>
References: <CHCErs.G5w@genesis.nred.ma.us> <2dj25i$1ga@u.cc.utah.edu>
NNTP-Posting-Host: bonnie.sax.de
In <2dj25i$1ga@u.cc.utah.edu> terry@cs.weber.edu (A Wizard of Earth C) writes:
>[ ... DMA problems with FDC ... ]
>It is probably your cache. ...
>... device initiated DMA has the potential
>to update memory without updating cache (on reads) or write data that is
>valid in cache but not in memory (unless your cache is write through) on
>writes.
Umm, Terry, i think you failed here.
The FDC does not do any ``device initiated DMA'' in this sense. It's simply
using the DMA chipset feature. This *should* not conflict with cache usage -
or the chipset design is broken. [We do not speak about SCSI host adaptors
that do bus-master DMA.]
In fact, i'm also experiencing lotta DMA overruns when attempting to do
some floppy IO while some heavy compile job is running. This is in a box
with an Adaptec SCSI, and i didn't track it down whether it's the CPU
load that causes the trouble (would really look strange to me), or if
it's the heavy disk IO that happens while compiling.
Assuming it's the latter, so it could be some problem with the host adaptor
DMA cycles - does the adaptec really care for other DMA requests floating
around on the bus while it is considering to take over the bus?
As a workaround, Serge Vakulenko proposed to simply ignore the DMA overrun
error and retry the transfer until it succeeds (or some other error occurs).
--
in real life: J"org Wunsch | ) o o | primary: joerg_wunsch@tcd-dresden.de
above 1.8 MHz: DL 8 DTL | ) | | private: joerg_wunsch@uriah.sax.de
| . * ) == |
``An elephant is a mouse with an operating system.''