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From: jmonroy@netcom.com (Jesus Monroy Jr)
Subject: Re: [FreeBSD 1.0R] DMA Problems?
Message-ID: <jmonroyCIJFAr.Atn@netcom.com>
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References: <CHCErs.G5w@genesis.nred.ma.us> <2dj25i$1ga@u.cc.utah.edu> <2encotINN3sq@bonnie.sax.de> <2eqjt7$dqm@u.cc.utah.edu> <CI6291.HBA@genesis.nred.ma.us> <2fbvtoINNk71@bonnie.sax.de>
Date: Fri, 24 Dec 1993 11:44:50 GMT
Lines: 102
J Wunsch (j@uriah.sax.de) wrote:
: steve2@genesis.nred.ma.us writes:
: >I originally asked the question so hopefully I can clarify things a bit.
: >>... BECAUSE the floppy does
: >>*not* _ALSO_ use DMA, ...
: [This statement is totally WRONG. It's just the opposite: only the floppy
: uses DMA by default. The dRAM refresh in an AT is no more done by a DMA
: channel, and the typical AT hard disk uses programmed IO by the CPU. The
: only one else using DMA (as bus-mastered DMA) are SCSI host adaptors.]
:
Beeeep.... Sorry Doctor Bob, contestant #1 has scored an
an incorrect point....... (so much for a try at humor) :-}
Seriously, the quesiton about DMA RAM refresh has an answer.
This was posted many moons ago as described below.
======================================================================
Released to: comp.os.os2.programmer.misc comp.os.linux.development
comp.os.minix comp.periphs comp.unix.bsd comp.unix.pc-clone.32bit
comp.sys.ibm.pc.hardware comp.sys.ibm.ps2.hardware
comp.os.386bsd.development
Released as: Test of the Intel 8254 shut-down/parity-check command
Released :00:07:44 Wed 09-15-1993
Note: only 386bsd got the shell archive
This is a condensed version of the posting.
To get the rest, subscribe to comp.os.386bsd.development _or_
wait till shell archive is available via anonymouse ftp at
etext.archive.umich.edu : /pub/Zines/QIC-News
========================================================================
Test of the Intel 8254 shut-down/parity-check command
-----------------------------------------------------
version: 1.0.0
date: 09-14-1993
author: jmonroy@netcom.com
Purpose: Test the for parity errors by shutting down
the RAM refresh timer.
While looking for the reason for DMA overruns
in the development of an FDC driver for
386bsd, suggestions were made that shutting
down the timer has no effect on the system;
reasons for this varied.
Compiling: I have made the code transportable.
It has been tested with:
MSDOS
-----
Zortech Personal C v. 1.07
Turbo C v. 2.01
Microsoft Quick C v. 2.50
386BSD
------
GNU C++ v. 1.39
How this works.
---------------
Simply the program issue a command to change
to mode 4 (described in the notes) with a "count-down"
value of 0x0a0a (2,570). This is done to timers 1 and 2,
the RAM refresh timer and the speaker timer, respectively.
Timer 0 is left running because most OSes cannot operate
without a timer for the "deadloop".
What should happen.
-------------------
On most 286 systems nothing will happen till a
interrupt is generated (I.E., keyboard pressed) or a RAM
chip finally loses it's charge. At this point, some system
will hang for a long while, some will immediately parity
error.
On 386bsd expect a "csh" coredump followed by a
system panic. The system will then reboot. On some systems
a parity error will never register.
What does this prove?
---------------------
Namely that the RAM refresh is controllable via
the i8254 timer on the IBM/ISA architecture.
--
Jesus Monroy Jr jmonroy@netcom.com
Zebra Research
/386BSD/device-drivers /fd /qic /clock /documentation
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