Return to BSD News archive
Newsgroups: comp.os.386bsd.development Path: sserve!newshost.anu.edu.au!munnari.oz.au!sgiblab!swrinde!elroy.jpl.nasa.gov!decwrl!netcomsv!netcom.com!jmonroy From: jmonroy@netcom.com (Jesus Monroy Jr) Subject: Re: [FreeBSD 1.0R] DMA Problems? Message-ID: <jmonroyCIo4yD.1G5@netcom.com> Organization: NETCOM On-line Communication Services (408 241-9760 guest) X-Newsreader: TIN [version 1.2 PL1] References: <jmonroyCIB20s.FF8@netcom.com> <2f8kjq$ft2@u.cc.utah.edu> <jmonroyCIHJA2.oy@netcom.com> <2fl24q$jn2@u.cc.utah.edu> Date: Mon, 27 Dec 1993 00:49:25 GMT Lines: 69 I am sorry to report you conclusions are in correct. I will point these "incorrect" conclusions 1 by 1. If I have, however, mis understood you, please let me know. My intent is to pass correct information along on this technical issue, *not* start a one-upmanship. A Wizard of Earth C (terry@cs.weber.edu) wrote: : In article <jmonroyCIHJA2.oy@netcom.com> jmonroy@netcom.com (Jesus Monroy Jr) writes: : >: No. No way. Not a chance. : >: : > No to what?.... I mentioned three things... no to what? : No, the statement that "the 'RAM refresh' process had priority over the : 'FDC transfer'" is incorrect. : This statement is incorrect. On the IBM PC/AT/XT arch. The ram refresh has priority because the DMA chip, the i8237, by design gives priority (if programmed) to the lowest DMA channel request, channel 0. The programming information for the i8237 is available. If you don't have a copy of it I will be happy to send you a photo copy, please let me know. : >: The main interaction between memory refresh and DMA is that you can : >: kill memory off and parity error yourself to death by holding the bus : >: so long that refreshes get skipped. Dynamic RAM gets pissy when you : >: skip its refresh. 8-). : > my information says that you can skip a few "RAM refresh" : > cycles... what are you saying? : You can. Tell me: how do you allow "skipping", but deterministically : sufficient skipping for the potential well to discharge to the point : that the memory contents are no longer reliable? There is no hardware : "skip count"... DRAM refresh is not a realtime process which will : interrupt other things on your motherboard to safeguard your memory : contents. : I beleive you asked a question and answer it yourself. If I am correct and you want me to say yes to the answer to your questions, I do no understand you answer. If you answer is "there is not hardware 'skip count'." You are correct. To my knowledge there is no hardware skip count for any DRAM refresh hardware; not to date anyway. If your statement includes the premise that DRAM refresh is *not* a realtime process which *will* interrupt other "things" to safeguard your memory, this is incorrect - by the design for IBM PC/AT/XT (et. all). : How many you can skip is dependent on the chip and the bus rate and : the on-time for the refresh... in other words, how deep the potential : well is, how long it is charged on initial write, and how long it is : charged on each refresh. And there is *no* way to probe this from : software. : I disagree. In the PC world there are plenty of PD and shareware programs that reprogram the DMA facility to accomplish just what you stated is not possible. If you like, get the program I wrote test the DMA timer. The information for this was in the previous thread message. -- Jesus Monroy Jr jmonroy@netcom.com Zebra Research /386BSD/device-drivers /fd /qic /clock /documentation ___________________________________________________________________________