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From: j@uriah.sax.de (J Wunsch)
Newsgroups: comp.os.386bsd.development
Subject: Re: [FreeBSD 1.0R] DMA Problems?
Date: 1 Jan 1994 20:57:51 +0100
Organization: Private U**X site; member IN e.V.
Lines: 28
Message-ID: <2g4kjvINNnsf@bonnie.sax.de>
References: <CHCErs.G5w@genesis.nred.ma.us> <2dj25i$1ga@u.cc.utah.edu> <2encotINN3sq@bonnie.sax.de> <2eqjt7$dqm@u.cc.utah.edu> <CI6291.HBA@genesis.nred.ma.us> <2fbvtoINNk71@bonnie.sax.de> <jmonroyCIJFAr.Atn@netcom.com>
NNTP-Posting-Host: bonnie.sax.de
In <jmonroyCIJFAr.Atn@netcom.com> jmonroy@netcom.com (Jesus Monroy Jr) writes:
> Seriously, the quesiton about DMA RAM refresh has an answer.
[...]
> What does this prove?
> ---------------------
> Namely that the RAM refresh is controllable via
> the i8254 timer on the IBM/ISA architecture.
>
Yes. But this doesn't prove they do the refresh via an DMA channel zero
request. They simply continue using the timer...
Actually, i know of a sample hardware application that used DMA channel 0
to get fast i/o done on a DAC. They totally re-programmed the DMA channel,
without losing dRAM refresh. Maybe they didn't reprogram the timer, though.
It's been too long ago, i don't remember the exact things.
As another point, as far as i know, all of the modern chipsets avoid re-
freshing all the memory banks at the same time in order to reduce power
current peaks. They rather split the refresh cycles across the memory
banks. Tell me, how should the DMA channel achieve this?
--
in real life: J"org Wunsch | ) o o | primary: joerg_wunsch@tcd-dresden.de
above 1.8 MHz: DL 8 DTL | ) | | private: joerg_wunsch@uriah.sax.de
| . * ) == |
``An elephant is a mouse with an operating system.''