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Path: sserve!newshost.anu.edu.au!munnari.oz.au!foxhound.dsto.gov.au!fang.dsto.gov.au!myall.awadi.com.au!myall!blymn From: blymn@awadi.com.au (Brett Lymn (master of the siren)) Newsgroups: comp.os.386bsd.questions Subject: micro-code vs DMA (was Re: CDROM support) Date: 17 Jan 1994 12:39:50 GMT Organization: AWA Defence Industries Pty. Ltd. Lines: 41 Message-ID: <BLYMN.94Jan17230950@siren.awadi.com.au> References: <2g5qaq$ng0@u.cc.utah.edu> <DykkFc3w165w@oasys.pc.my> <BLYMN.94Jan9192240@siren.awadi.com.au> <2gs11p$58g@delphinium.cig.mot.com> NNTP-Posting-Host: siren.awadi.com.au In-reply-to: declrckd@rtsg.mot.com's message of 10 Jan 1994 16:51:05 GMT >>>>> "Dan" == Dan J Declerck <declrckd@rtsg.mot.com> writes: In article <2gs11p$58g@delphinium.cig.mot.com> declrckd@rtsg.mot.com (Dan J. Declerck) writes: Dan> In article <BLYMN.94Jan9192240@siren.awadi.com.au>, Brett Lymn Dan> (master of the siren) <blymn@awadi.com.au> wrote: Dan> The REP operation on Intel parts is similar to the DBcc operation Dan> on Motorola parts, in the effect that once this 2 instruction Dan> loop is fetched, no further opcode fetching takes place until it Dan> is complete. Also, you must remember that some systems have Dan> cache, which allow the processor many bus cycles for every DRAM Dan> memory cycle. This is true on every 486DX system. True, I did forget about the micro-code repeat instructions but IMHO my assertion still holds since there are a lot of provisos that go with the REP instruction (let's talk ix86 here, the same holds for 680x0 as well), for a start you lose big time if the target buffer does not exist in the TLB since you will suffer the overhead of a cache miss for each byte in the buffer. Also if you ignore the REP instruction startup time you are still hit 8 cycles for each time through the REP INS loop (this is minimum since the timing is based on a cache hit). Now if you assume that 1 cycle == 1 clock period (not necessarily true) then a 33MHz i486 would be able to do about 4MHz effective DMA, that is with a lot of assumptions as opposed to a 5MHz DMA rate (I think it's 5...). Dan> The BIOS for the original IBM AT uses NO DMA to interface to the Dan> drive controller. the 286 was faster thyan DMA for DOS (Unix is a Dan> different story). A lot of programmers have a mistrust of DMA, must be because it's a hardware fix ;-) For DOS there is little point in avoiding hogging the CPU with pointless tasks like transferring data from disk, in a multitasking system the CPU could be doing other things. I suppose that reflects itself in the low end interface hardware, cutting corners by not putting a DMAC on board, instead getting the CPU to do the grunt work. -- Brett Lymn