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Path: sserve!newshost.anu.edu.au!munnari.oz.au!bunyip.cc.uq.oz.au!harbinger.cc.monash.edu.au!yeshua.marcam.com!news.kei.com!nic.hookup.net!swrinde!cs.utexas.edu!uunet!Germany.EU.net!netmbx.de!zrz.TU-Berlin.DE!math.fu-berlin.de!news.tu-chemnitz.de!irz401!uriah!not-for-mail From: j@uriah.sax.de (J Wunsch) Newsgroups: comp.os.386bsd.development Subject: Re: [FreeBSD 1.0R] DMA Problems? Date: 17 Jan 1994 13:18:58 +0100 Organization: Private U**X site; member IN e.V. Lines: 63 Message-ID: <2hdvniINN1mu@bonnie.sax.de> References: <CHCErs.G5w@genesis.nred.ma.us> <2dj25i$1ga@u.cc.utah.edu> <2encotINN3sq@bonnie.sax.de> <2eqjt7$dqm@u.cc.utah.edu> <CI6291.HBA@genesis.nred.ma.us> <2fbvtoINNk71@bonnie.sax.de> <jmonroyCIJFAr.Atn@netcom.com> <2g4kjvINNnsf@bonnie.sax.de> <jmonroyCJ3ts3.1Ls@netcom.com> <2gk4fjINNal@bonnie.sax.de> <jmonroyCJB69t.D8B@netcom.com> <2gumo6INNi85@bonnie.sax.de> <jmonroyCJIroC.6AG@netcom.com> NNTP-Posting-Host: bonnie.sax.de jmonroy@netcom.com (Jesus Monroy Jr) writes: > Can I clear this up by sending you a copy of the > page in the IBM technical reference where "what I assume" > is stated? Though i don't own any IBM box, yes, you can... As long as it ain't more thant say 20 KB. I'm only uucp-connected and have to pay real money for each byte. (That's why i hate your indented text. Band width without any information at all.) > OK... in English then, you disabled the controller > chip, via the Command REgister .. > the DMA refresh is a psuedo operation. > meaning that it does not do a read or a write - btw., it does a read, but throws away the byte read > - simply a strobe of the address line. Yes. But it will have to initiate a bus cycle to do this. If i'm disabling my DMA controller, it cannot initiate anything. So it's irrelevant whether this is a dummy operation or not. The term ``dummy'' only refers to the fact here that there is no data transferred. But not to the fact the DMA would not be needed anymore. If i kill any DMA operation, i would also kill the dRAM refresh if it were done by DMA. >: I've stated all the results of my test. (DMA fails, but RAMs are okay.) >: > No, what you stated were the conclusions of your test. What else results did you expect? > I think you're being stubborn or lazy. The latter, definately. >: I can >: simply stop it with some out's from my debugger. >: > I don't think your serious. Why not? Any good debugger might be much more helpful than tons of code lines. I would never have completed my old CP/M floppy driver without extended tests run through a debugger. (The only thing on floppies that cannot be done by a debugger is sector read/write, since it implies tight timing conditions. Everything else, up to a READ SECTOR ID can be done with a debugger.) >: DMA channel 0 is not wired to the IO bus, thus it is only available for >: mainboard chips (if there are any). >: > Wait a minute... here in a previous article you stated > that some (support) boards can use DMA channel 0!! Aeh, well, i should have looked into that old magazine... But sorry, i don't have the time for it, and i think it wouldn't bring us any millimeter closer to a solution of our DMA overrun problem. -- in real life: J"org Wunsch | ) o o | primary: joerg_wunsch@tcd-dresden.de above 1.8 MHz: DL 8 DTL | ) | | private: joerg_wunsch@uriah.sax.de | . * ) == | ``An elephant is a mouse with an operating system.''