*BSD News Article 26390


Return to BSD News archive

Xref: sserve comp.os.386bsd.development:1712 comp.sys.ibm.pc.hardware.chips:1881 comp.periphs:4942
Path: sserve!newshost.anu.edu.au!munnari.oz.au!bunyip.cc.uq.oz.au!harbinger.cc.monash.edu.au!yeshua.marcam.com!usc!sdd.hp.com!col.hp.com!csn!hellgate.utah.edu!cc.usu.edu!ivie
From: ivie@cc.usu.edu
Newsgroups: comp.os.386bsd.development,comp.sys.ibm.pc.hardware.chips,comp.periphs
Subject: Re: The DMA problem again!
Message-ID: <1994Jan22.120513.8484@cc.usu.edu>
Date: 22 Jan 94 12:05:12 MDT
References: <jmonroyCJxHBH.2x0@netcom.com>
Followup-To: comp.os.386bsd.development,comp.sys.ibm.pc.hardware.chips,comp.periphs
Organization: Utah State University
Lines: 46

In article <jmonroyCJxHBH.2x0@netcom.com>, jmonroy@netcom.com (Jesus Monroy Jr) writes:
>             1)  The RAM refresh is controlled, on many AT-type machines,
>                 by the DMA controller on channel 0 and the (PIT) Timer on
>                 channel 1.

OK, I've found my copy of IBM's "Technical Reference, Personal Computer AT".
Let's take a look at the schematics.

On sheet 14, we see the DMA controllers. DMA channel 4 is used to cascade
the DMA controllers. The rest of the DMA requests and acknowledges go to
sheets 19 and 20, where they are placed on the connectors; channels 1, 2, and
3 are on the PC connector and channels 0, 5, 6, and 7 are on the AT connector.

In other words, DMA channel 0 is not involved in refresh.

Over on sheet 21, we see the circuitry that performs refreshes. The Hold
ReQuests from the DMA controllers come into this circuitry, which sits between
the DMA controllers and the CPU. Yes, timer channel 1 is involved.

>             2)  Devices like the FDC (floppy drive controller) make
>                 abundant use of this facility and would make good
>                 test platform since most people have them on there
>                 PC type machines.

I, for one, would be very surprised if you could convince the FDC to hang
onto the bus long enough to make the motherboard miss a refresh cycle.
A floppy is running at 500KHz for high density. That's roughly 50K 
bytes/second (I said "roughly"). In order to make the motherboard miss a
refresh cycle, the DMA controller must:

	1) Acquire the bus. Floppies can make it do this.
and
	B) Hold onto the bus long enough for a refresh cycle to be missed.
	   The floppies _can't_ do _this_.

In order to hold onto the bus for a long time, you need to:

	A) Be a bus mastering controller.
or
	II) Do a long burst DMA.

Neither of which the floppy controller can do.
-- 
----------------+------------------------------------------------------
Roger Ivie      | Don't think of it as a 'new' computer, think of it as
ivie@cc.usu.edu |     'obsolete-ready'