Return to BSD News archive
Xref: sserve comp.os.386bsd.development:1719 comp.sys.ibm.pc.hardware.chips:1910 comp.periphs:4946 Newsgroups: comp.os.386bsd.development,comp.sys.ibm.pc.hardware.chips,comp.periphs Path: sserve!newshost.anu.edu.au!munnari.oz.au!bunyip.cc.uq.oz.au!harbinger.cc.monash.edu.au!yeshua.marcam.com!usc!elroy.jpl.nasa.gov!decwrl!netcomsv!netcom.com!jmonroy From: jmonroy@netcom.com (Jesus Monroy Jr) Subject: Re: The DMA problem again! Message-ID: <jmonroyCK4tFo.3Jx@netcom.com> Organization: NETCOM On-line Communication Services (408 241-9760 guest) X-Newsreader: TIN [version 1.2 PL1] References: <jmonroyCJxHBH.2x0@netcom.com> <1994Jan22.120513.8484@cc.usu.edu> Date: Mon, 24 Jan 1994 11:33:24 GMT Lines: 78 ivie@cc.usu.edu wrote: : In article <jmonroyCJxHBH.2x0@netcom.com>, jmonroy@netcom.com (Jesus Monroy Jr) writes: : > 1) The RAM refresh is controlled, on many AT-type machines, : > by the DMA controller on channel 0 and the (PIT) Timer on : > channel 1. : OK, I've found my copy of IBM's "Technical Reference, Personal Computer AT". : Let's take a look at the schematics. : Wonderful.... let's see if you can read. : On sheet 14, we see the DMA controllers. DMA channel 4 is used to cascade : Sheet 14? OK... I see two big chips "U111" and "U122" correct? : the DMA controllers. : Yes, I see the chips marked as 8237a-5. Correct? : The rest of the DMA requests and acknowledges go to : sheets 19 and 20, where they are placed on the connectors; : I see that the DMA circuit-wires go to sheets 15,19 and 20; of which sheets 19 and 20 have diagrams for the ISA bus connector. (wonderful... we confirmed the known... please excuse the sarcasium.) : channels 1, 2, and : 3 are on the PC connector and channels 0, 5, 6, and 7 are on the AT connector. : Yes, the DACK channels 0, 5, 6, and 7 are connected to the 36 pin bus. : In other words, DMA channel 0 is not involved in refresh. : From the facts you have previously stated, no logic can be derived to state DMA channel 0 is not involved in the refresh. Plainly, you have not made a point... perhaps you forgot to mention something _or_ you've missed something. Please clarify how you concluded that channel 0 is not involved in "refresh". : Over on sheet 21, we see the circuitry that performs refreshes. The Hold : ReQuests from the DMA controllers come into this circuitry, which sits between : the DMA controllers and the CPU. Yes, timer channel 1 is involved. : Marvelous... (some people will say you have stated the obvious, I will say: you doing the work.) : > 2) Devices like the FDC (floppy drive controller) make : > abundant use of this facility and would make good : > test platform since most people have them on there : > PC type machines. : I, for one, would be very surprised if you could convince the FDC to hang : onto the bus long enough to make the motherboard miss a refresh cycle. : This makes two of us... I don't think I've ever stated that the FDC can hang the "refresh". I am saying the inverse (or is it the converse, anyhow). I beleive the DMA RAM refresh signal is interfering with the FDC transfer. : :: [deleted assumed incorrect definition of problem] :: : What point were you trying to make? -- Jesus Monroy Jr jmonroy@netcom.com Zebra Research /386BSD/device-drivers /fd /qic /clock /documentation ___________________________________________________________________________