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From: fred@genesis.demon.co.uk (Lawrence Kirby)
Path: sserve!newshost.anu.edu.au!munnari.oz.au!news.Hawaii.Edu!ames!decwrl!nic.hookup.net!swrinde!cs.utexas.edu!howland.reston.ans.net!pipex!demon!dis.demon.co.uk!genesis.demon.co.uk!fred
Subject: Re: The DMA problem again!
References: <jmonroyCJxHBH.2x0@netcom.com> <1994Jan22.120513.8484@cc.usu.edu> <jmonroyCK4tFo.3Jx@netcom.com> <CK5AoL.6LL@ucdavis.edu>
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Reply-To: fred@genesis.demon.co.uk
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Date: Mon, 24 Jan 1994 23:43:19 +0000
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In article <CK5AoL.6LL@ucdavis.edu>
fzshenau@dale.ucdavis.edu "Greg Shenaut" writes:
.
.
>Now the _probability_ of this kind of delay occuring as a result of a
>refresh cycle is much lower due to the low frequency of refresh cycles,
>but I think that it may be _possible_.
It depends how long a refresh cycle can tie up the bus.
It seems to be a general thing that bus master controllers stop interfering
with floppy transfers when you reduce the bus-on time to about 7us or less.
I would have thought a refresh cycle would be much shorter than this.
-----------------------------------------
Lawrence Kirby | fred@genesis.demon.co.uk
Wilts, England | 70734.126@compuserve.com
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