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From: j@uriah.sax.de (J Wunsch)
Newsgroups: comp.os.386bsd.development,comp.periphs
Subject: Re: Restart of discussion on the DMA problem.
Date: 28 Jan 1994 12:07:30 +0100
Organization: Private U**X site; member IN e.V.
Lines: 20
Message-ID: <2iarliINN4ih@bonnie.sax.de>
References: <jmonroyCK8tAL.4GD@netcom.com>
NNTP-Posting-Host: bonnie.sax.de

jmonroy@netcom.com (Jesus Monroy Jr) writes:

>		I will admit that the DRAM (not SRAM, not VRAM) is refreshed
>	via timer 1 with the Intel 8254 PIT (Programmable Interrupt Timer).
> 
>		I will admit that I (on occasion) have enumerated DMA channel 0
>	as being an element in the DRAM refresh; this is not correct.
>	Correctly, DMA channel 0 is not directly involved in the DRAM refresh
>	on the IBM PC-AT (or 100% compatibles).

Sigh! Now you believe it. Sorry, i don't have an IBM reference manual,
but the above is all i'd like to prove you with my experiments. And you'd
really need a debugger to prove this...

Btw., _my_ DMA overruns appear to be really Adaptec-related.
-- 
in real life: J"org Wunsch |   )  o o  | primary: joerg_wunsch@tcd-dresden.de
above 1.8 MHz:   DL 8 DTL  |    )  |   | private: joerg_wunsch@uriah.sax.de
                           | . * ) ==  |
          ``An elephant is a mouse with an operating system.''