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Xref: sserve comp.unix.bsd:2853 comp.os.linux:6584 comp.periphs.scsi:6408 Newsgroups: comp.unix.bsd,comp.os.linux,comp.periphs.scsi Path: sserve!manuel!munnari.oz.au!sgiblab!sdd.hp.com!cs.utexas.edu!uunet!mcsun!sun4nl!relay.philips.nl!philica!adrie From: adrie@ica.philips.nl (Adrie Koolen) Subject: Re: Query: Drivers for AHA >1522< ? Message-ID: <1992Jul31.064243.983@ica.philips.nl> Organization: Philips Consumer Electronics, Eindhoven, The Netherlands References: <14hjqoINNr78@agate.berkeley.edu> <1992Jul23.232138.20172@colorado.edu> <1992Jul29.204834.20882@adaptx1.UUCP> Date: Fri, 31 Jul 1992 06:42:43 GMT Lines: 40 In article <1992Jul29.204834.20882@adaptx1.UUCP> neese@adaptx1.UUCP (Roy Neese) writes: >In article <1992Jul23.232138.20172@colorado.edu> drew@ophelia.cs.colorado.edu (Drew Eckhardt) writes: >> If you're talking about sustained transfer rate, it's going to be >> faster to do polled I/O because you don't have the couple of clock >> cycles associated with each bus on period - you just crank data >> across the AT bus topspeed, 16 bits at a time. > >Nope. Polled I/O can never be faster than bus master DMA as it takes >twicw as many cycles to move each word doing polled I/O as it does for a >bus master to move the same word. >The overhead you speak of is for acquiring the bus, wchi takes 2 cycles >and then of course it takes another 2 cylces to release the bus. But to >show a more subjective view. Let's make some assumptions, good >assumptions. Let's say 1 cycle per word for bus master DMA and 2 cycles >per word for polled I/O (you have to do a read and write for polled I/O, >whereas bus masters do either a read or a write). Now let's move 512 >bytes of data. Let's see,... for polled that would be 1024 cycles and >for a bus master 512 + 2 + 2 = 516. Nuff' said. Unless I misunderstand the conditions of your example transfer, I have to disagree. I assume that you mean "AT-bus cycle" when you talk about cycles. Clearly, you can't transfer one word over the AT-bus in only one cycle. I was under the impression that it takes some 6 or 8 cycles. That would seem to be a bigger advantage for bus mastering controllers, but you're wrong in the assumption that the write into (or read from) memory is done over the AT-bus. Normally, this is done over the local CPU bus (33 MHz?), which is much faster than the AT-bus (8 MHz?). Furthermore, it would be unwise to take the AT-bus for 512 cycles. Under normal 1542b operation, the bus freed after some 7 cycles, so the overhead of getting and releasing the bus is bigger. I agree that bus mastering I/O is faster than polled I/O over the AT-bus, but not with the factor you indicate. Adrie Koolen (adrie@ica.philips.nl) Philips Consumer Electronics, Eindhoven, the Netherlands