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From: eld@keyhole.ucsd.edu (Eric Dorman)
Newsgroups: comp.os.386bsd.questions
Subject: Re: 386 VS 286
Date: 12 Apr 1994 00:44:02 -0700
Organization: MPL of SIO at UCSD
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From chiyoko@knight.ice.sda.cbis.com Tue Apr 12 00:31:42 PDT 1994
>Do the 286 processors use translation lookaside buffers (TLBs)?
'286s have no on-board facilities for managing virtual pages. It does
implement a segmentation scheme a segment register points
to a table held in core where the protection and physical
address data live. When a segment register is first loaded
the processor reads the corresponding segment table entry into
a cache onboard the chip, so in a sense this could be called a TLB.
>What type of write polyicy does a typical 286 processor implement?
As far as I know no commercial segmented-VM system was ever released
for the '286s. It's really not that hard to implement (i've done it)
but it seemed that people were more interested in whining about the
'286s architecture than writing programs that worked :) On my hardware
there wasn't any problems with disk/memory coherency so all seg-writes
were delayed ('cept for some special cases).
>Are there any references comparing a segmented memory model and
>a linear flat memory model?
You might look at some of the late '80s issues of Byte; i recall
there being a reasonable comparison between 286/386 in there somewhere.
Sorry I don't have a more precise reference! :)
>Pardon me for the ancient subject but I have not worked on Intel processors
>before.
Intel architectures are character-building!
>Chiyoko Koike Miklasevich
Eric Dorman
eld@mpl.ucsd.edu
eric@siodept.ucsd.edu