*BSD News Article 37406


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From: rob@pe1chl.ampr.org (Rob Janssen)
Subject: Re: 16550 detection
Reply-To: pe1chl@rabo.nl
Organization: PE1CHL
Message-ID: <CyntLn.HD@pe1chl.ampr.org>
References: <CMETZ.94Oct30051603@itchy.inner.net>  <SRA.94Oct30162124@rurha-pente.epilogue.com>  <CMETZ.94Oct30192816@itchy.inner.net> <CyIzxz.97A@cuug.ab.ca>  <TYTSO.94Oct31162517@dcl.mit.edu>  <MICHAELV.94Oct31211019@MindBender.HeadCandy.com> <TYTSO.94Nov1182557@dcl.mit.edu> <396p13$d0n@news.ycc.yale.edu>
Date: Wed, 2 Nov 1994 21:41:47 GMT
Lines: 38

In <396p13$d0n@news.ycc.yale.edu> news@remote1-line2.cis.yale.edu (Marc's News Account) writes:

>In article <TYTSO.94Nov1182557@dcl.mit.edu>, tytso@athena.mit.edu (Theodore Y. Ts'o) writes:
>|> In article <MICHAELV.94Oct31211019@MindBender.HeadCandy.com> michaelv@MindBender.HeadCandy.com (Michael L. VanLoon) writes:
>|> >You make a lot of generalizations about 16550-like UARTs that aren't
>|> >the real thing and have 1024-byte pseudo buffers.  I don't know what
>|> >you're talking about since I've never seen such a thing.
>|> 

>|> However, if you're using your Hayes ESP card in 16550 compatibility
>|> mode, you're probably not really taking much advantage of your 1024 byte
>|> FIFO.  It looks good, and sounds sexy; but is actually practical?
>|> Probably not.

>This is a good point and leads to a question I would like to ask Mr. VanLoon -
>given that a 1K buffer does seem a bit excessive for a standard 16550, does the
>Hayes ESP card do anything nifty, like FM-0 encoding (230.4Kbps, aka LocalTalk)? 
>If so, will they tell me how to program it?  If this is so, I would be very
>interested in such a card. Z85C30's I believe have a similar FIFO as well, and
>they're pretty powerful USARTs

The Z85C30 is a powerful chip that can do a lot more than a 16450, but the
FIFO is not particularly good.  It has a 3-byte FIFO on receive, and only
one byte on transmit.
The Z85230 is a version with a deeper FIFO (8 bytes on receive, 4 bytes on
transmit), but it is still not as clever as the 16550A.  It cannot be
programmed to send one interrupt when the FIFO's exceed a threshold
(e.g. half-full) and still interrupt when nothing comes in for some time.

Anyway, these chips are good when HDLC and/or encoding (like NRZI or FM-0)
is required, but are not especially well suited for plain ASYNC.

Rob
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| Rob Janssen                | AMPRnet:   rob@pe1chl.ampr.org           |
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