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Path: sserve!newshost.anu.edu.au!harbinger.cc.monash.edu.au!simtel!news.kei.com!news.mathworks.com!solaris.cc.vt.edu!ceharris From: ceharris@mal.com (Carl Harris) Newsgroups: comp.unix.bsd.freebsd.misc Subject: Re: IRQ 9 unsafe? Date: 6 Jul 1995 10:38:32 GMT Organization: Maladjusted Communications Lines: 35 Message-ID: <3tgef8$ffn@solaris.cc.vt.edu> References: <gztQkHQ@quack.kfu.com> <3t940q$cf4@anshar.shadow.net> <3tc4dn$9k2@csugrad.cs.vt.edu> Reply-To: ceharris@mal.com NNTP-Posting-Host: mal9000.mal.com NNTP-Posting-User: ceharris X-Newsreader: TIN [version 1.2 PL2] Jeff Aitken (jaitken@csugrad.cs.vt.edu) wrote: : Don Whiteside (dwhite@anshar.shadow.net) wrote: : : IRQ 9 is indeed a cascaded IRQ 2. : Pardon my ignorance, but what exactly does that mean? In the original IBM PC, there was only one peripheral interrupt controller, or PIC -- an Intel 8259A. For all practical purposes, every one of the available IRQ lines on that PIC were reserved (clock tick, keyboard, COM1, COM2, floppy disk, hard disk, LPTx) except IRQ 2, which was "reserved by IBM." Needless to say, this situation made it devilishly difficult to put anything else that needed an interrupt line into the machine. So when the AT was designed, IBM added a second PIC (also an 8259A chip). (Then IBM went on to reserve a good many of those IRQs. ;-\ ) Since, in general, there is only one external (maskable) interrupt input line on a CPU, only one PIC can be attached directly to it. The 8259A was designed to solve this problem by allowing cascading. In a cascaded configuration, the PIC's INT line (which indicates that an interrupt is pending on one of its IRQ lines) is attached to an IRQ pin on another PIC. In the case of the AT, the second PIC's INT pin is attached to the first controller's IRQ 2 pin. I don't have my Intel chip handbook handy, and I don't recall if there was something magical about using IRQ 2 for the cascaded controller, or whether IBM chose IRQ 2 because they hadn't already used it for something else. -- Carl Harris EXECUTIVE Scapegoat (and Systems Engineer) ceharris@mal.com http://www.mal.com/~ceharris