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Newsgroups: comp.unix.bsd
Path: sserve!manuel!munnari.oz.au!uunet!elroy.jpl.nasa.gov!ames!ictv!barry
From: barry@ictv.com (Barry Lustig)
Subject: Re: /386bsd: reject 65340
Message-ID: <1992Sep20.202359.1360@ictv.com>
Sender: usenet@ictv.com
Organization: ICTV, Santa Clara, CA (408) 562-9200
References: <q1vejko@sgi.sgi.com>
Date: Sun, 20 Sep 1992 20:23:59 GMT
Lines: 233
In article <q1vejko@sgi.sgi.com> rpw3@rigden.wpd.sgi.com (Rob Warnock) writes:
I was doing fine with my WD8013 "Combo" until I applied Barry Lustig's
patch to turn on 16-bit transfers. Then the "reject"s started:
Sep 19 04:33:01 jolly /386bsd: reject 65531reject 65531reject 65531
Sep 19 04:33:01 jolly /386bsd: reject 65531
...
I had to back out the change. (Barry? *Help!*)
-Rob
p.s. My config line:
device we0 at isa? port 0x280 net irq 2 iomem 0xd0000 iosiz 8192 vector weintr
p.p.s. Late flash: It looks like perhaps some bits of "laar.laar_byte" are
used but never initialized... What should they be set to? (0?)
Sorry about the goof folks. laar.laar_byte and wem.ms_byte should
both be initialized to 0 before use. Otherwise, who knows what bits
are getting set. Put the following 2 lines into weprobe just after
the variable declarations.
wem.ms_byte = 0;
laar.laar_byte = 0;
Just in case, I'll include the whole patch again. This patch is
against virgin copies of the 2 files if_we.c and if_wereg.h.
CUT HERE
===================================================================
RCS file: /CVSROOT/386BSD/src/sys.386bsd/i386/isa/if_we.c,v
retrieving revision 1.1
diff -c -r1.1 if_we.c
*** /tmp/,RCSt1000532 Sun Sep 20 14:21:13 1992
--- if_we.c Fri Sep 18 11:15:01 1992
***************
*** 136,142 ****
--- 136,146 ----
register int i;
register struct we_softc *sc = &we_softc[is->id_unit];
union we_mem_sel wem;
+ union we_laar laar;
u_char sum;
+
+ wem.ms_byte = 0;
+ laar.laar_byte = 0;
/* reset card to force it into a known state. */
outb(is->id_iobase, 0x80);
***************
*** 145,150 ****
--- 149,162 ----
/* wait in the case this card is reading it's EEROM */
DELAY(5000);
+ #if defined(WD8013)
+ /* allow the NIC to access the shared RAM 16 bits at a time */
+
+ laar.addr_l19 = 1;
+ laar.lan_16_en = 1;
+ laar.mem_16_en = 1;
+ outb(is->id_iobase+5, laar.laar_byte); /* Write a 0xc1 */
+ #endif
/*
* Here we check the card ROM, if the checksum passes, and the
* type code and ethernet address check out, then we know we have
***************
*** 164,169 ****
--- 176,182 ----
return (0);
#endif
/*printf("type %x ", sc->we_type);*/
+
if (sc->we_type & WD_SOFTCONFIG) {
int iv = inb(is->id_iobase + 1) & 4 |
((inb(is->id_iobase+4) & 0x60) >> 5);
***************
*** 173,178 ****
--- 186,192 ----
outb(is->id_iobase+4, inb(is->id_iobase+4) | 0x80);
}
+
/*
* Setup card RAM area and i/o addresses
* Kernel Virtual to segment C0000-DFFFF?????
***************
*** 296,302 ****
weinit(unit);
}
! static Bdry;
/*
* Initialization of interface (really just DS8390).
*/
--- 310,316 ----
weinit(unit);
}
! static Bdry[NWE]; /* Need one of these per device -mng 920811 */
/*
* Initialization of interface (really just DS8390).
*/
***************
*** 320,332 ****
* this is stock code...please see the National manual for details.
*/
s = splhigh();
! Bdry = 0;
wecmd.cs_byte = inb(sc->we_io_nic_addr + WD_P0_COMMAND);
wecmd.cs_stp = 1;
wecmd.cs_sta = 0;
wecmd.cs_ps = 0;
outb(sc->we_io_nic_addr + WD_P0_COMMAND, wecmd.cs_byte);
outb(sc->we_io_nic_addr + WD_P0_DCR, WD_D_CONFIG);
outb(sc->we_io_nic_addr + WD_P0_RBCR0, 0);
outb(sc->we_io_nic_addr + WD_P0_RBCR1, 0);
outb(sc->we_io_nic_addr + WD_P0_RCR, WD_R_MON);
--- 334,351 ----
* this is stock code...please see the National manual for details.
*/
s = splhigh();
! Bdry[unit] = 0;
wecmd.cs_byte = inb(sc->we_io_nic_addr + WD_P0_COMMAND);
wecmd.cs_stp = 1;
wecmd.cs_sta = 0;
wecmd.cs_ps = 0;
outb(sc->we_io_nic_addr + WD_P0_COMMAND, wecmd.cs_byte);
+ #if defined(WD8013)
+ /* enable 16 bit access if 8013 card */
+ outb(sc->we_io_nic_addr + WD_P0_DCR, WD_D_CONFIG16);
+ #else
outb(sc->we_io_nic_addr + WD_P0_DCR, WD_D_CONFIG);
+ #endif
outb(sc->we_io_nic_addr + WD_P0_RBCR0, 0);
outb(sc->we_io_nic_addr + WD_P0_RBCR1, 0);
outb(sc->we_io_nic_addr + WD_P0_RCR, WD_R_MON);
***************
*** 429,436 ****
union we_command wecmd;
union we_interrupt weisr;
- unit =0;
-
/* disable onboard interrupts, then get interrupt status */
wecmd.cs_byte = inb(sc->we_io_nic_addr + WD_P0_COMMAND);
wecmd.cs_ps = 0;
--- 448,453 ----
***************
*** 516,523 ****
wecmd.cs_ps = 1;
outb(sc->we_io_nic_addr + WD_P0_COMMAND, wecmd.cs_byte);
curr = inb(sc->we_io_nic_addr + WD_P1_CURR);
! if(Bdry)
! bnry =Bdry;
while (bnry != curr)
{
--- 533,540 ----
wecmd.cs_ps = 1;
outb(sc->we_io_nic_addr + WD_P0_COMMAND, wecmd.cs_byte);
curr = inb(sc->we_io_nic_addr + WD_P1_CURR);
! if(Bdry[unit])
! bnry =Bdry[unit];
while (bnry != curr)
{
***************
*** 561,567 ****
outb(sc->we_io_nic_addr + WD_P0_COMMAND, wecmd.cs_byte);
curr = inb(sc->we_io_nic_addr + WD_P1_CURR);
}
! Bdry = bnry;
}
/*
--- 578,584 ----
outb(sc->we_io_nic_addr + WD_P0_COMMAND, wecmd.cs_byte);
curr = inb(sc->we_io_nic_addr + WD_P1_CURR);
}
! Bdry[unit] = bnry;
}
/*
===================================================================
RCS file: /CVSROOT/386BSD/src/sys.386bsd/i386/isa/if_wereg.h,v
retrieving revision 1.1
diff -c -r1.1 if_wereg.h
*** /tmp/,RCSt1000536 Sun Sep 20 14:21:14 1992
--- if_wereg.h Mon Aug 31 11:09:34 1992
***************
*** 56,61 ****
--- 56,78 ----
};
/*
+ * LA Address Register (LAAR)
+ */
+ union we_laar {
+ struct lan_addr_reg {
+ u_char addr_l19_b:1, /* Address Line 19 for enabling */
+ /* 16 bit NIC access to shared RAM */
+ unused_b:5, /* unused (or unknown) bits */
+ lan_16_en_b:1, /* Enables 16bit shrd RAM for LAN */
+ mem_16_en_b:1; /* Enables 16bit shrd RAM for host */
+ } laar_decode;
+ #define addr_l19 laar_decode.addr_l19_b
+ #define lan_16_en laar_decode.lan_16_en_b
+ #define mem_16_en laar_decode.mem_16_en_b
+ u_char laar_byte; /* entire byte */
+ };
+
+ /*
* receive ring discriptor
*
* The National Semiconductor DS8390 Network interface controller uses
***************
*** 235,240 ****
--- 252,258 ----
#define WD_D_FT1 0x40 /* Fifo Threshold Select */
#define WD_D_RES 0x80 /* reserved... */
#define WD_D_CONFIG (WD_D_FT1|WD_D_BMS)
+ #define WD_D_CONFIG16 (WD_D_FT1|WD_D_BMS|WD_D_LAS|WD_D_WTS)
/*
* Configuration constants (interrupt mask register)
--