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Path: euryale.cc.adfa.oz.au!newshost.anu.edu.au!harbinger.cc.monash.edu.au!news.mel.connect.com.au!munnari.OZ.AU!news.ecn.uoknor.edu!news.cis.okstate.edu!news.ksu.ksu.edu!hptemp1.cc.umr.edu!news.missouri.edu!zombie.ncsc.mil!news.mathworks.com!newsfeed.internetmci.com!EU.net!Germany.EU.net!Dortmund.Germany.EU.net!nntp.gmd.de!news.rwth-aachen.de!news.rhrz.uni-bonn.de!RRZ.Uni-Koeln.DE!zpr.uni-koeln.de!se From: se@ZPR.Uni-Koeln.DE (Stefan Esser) Newsgroups: comp.unix.bsd.freebsd.misc Subject: Re: ASUS SP3G PCI chipset settings.. Date: 30 Jan 1996 14:48:04 GMT Organization: Institute for Mathematics, University of Cologne, Germany Lines: 59 Sender: se@Sysiphos (Stefan Esser) Message-ID: <4elb34$l7i@news.rrz.uni-koeln.de> References: <4efdo1$8oc@nntp5.u.washington.edu> NNTP-Posting-Host: sysiphos.mi.uni-koeln.de In article <4efdo1$8oc@nntp5.u.washington.edu>, caj@tower.stc.housing.washington.edu (Craig Johnston) writes: |> Under FreeBSD with this motherboard, which of the settings under |> chipset config for the motherboard can one enable? |> |> What is 'PCI posted write' and should I enable it? Posted write means that there is a FIFO between the CPU and the PCI bus. The CPU doesn't have to way for the data to arrive at its destination. Then there is the PCI burst mode, which allows sending multiple data words to consecutive memory addresses using a faster bus protocol. Only the first address is sent over the bus, the device is responsible for incrementing the addresses for all following data words. |> Should I enable all the various PCI buffering? Yes. The SP3G works reliably with all of the enabled. |> I have read that ISA GAT should be turned off. It seems to cause problems with some ISA cards, especially sound cards, if enabled. |> Don't you wish manufacturers would document this stuff a bit? Its all documented in the Intel Saturn technical data book. Ask your nearest Intel representative :) |> I'm running the latest version of the flash BIOS available, and |> I do have the dirty-tag-sram-whatever-it-is-called installed on my |> mboard. I've read this is necessary to use the board in write-back |> mode.. ? The board comes with write-back secondary cache set as the default. But with no Dirty Tag RAM, there is much useless copy back activity. Suchh a system is slower than one with a write-through secondary cache, in fact. If you got a the Tag RAM, then you'll see some 3% to 5% performance gain with write-back, compared to write-through. |> Any recommend settings, tweaks for this board? PCI latencies, etc? |> I've got an AMD dx4-100 in it. The latency timer just limits the timeslice of a PCI bus master controller, in case of competition for the bus ... This is to prevent one device from locking out all other PCI chips from the bus for too long. If you didn't get many bus-master PCI cards, it doesn't make any difference at all. Regards, STefan -- Stefan Esser, Zentrum fuer Paralleles Rechnen Tel: +49 221 4706021 Universitaet zu Koeln, Weyertal 80, 50931 Koeln FAX: +49 221 4705160 ============================================================================== http://www.zpr.uni-koeln.de/~se <se@ZPR.Uni-Koeln.DE>