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Path: sserve!manuel!munnari.oz.au!hp9000.csc.cuhk.hk!uakari.primate.wisc.edu!news.larc.nasa.gov!darwin.sura.net!spool.mu.edu!agate!doc.ic.ac.uk!uknet!mcsun!sunic!sics.se!jonas From: jonas@sisu.se (Jonas Lagerblad) Newsgroups: comp.unix.bsd Subject: Hardware (cache) problem on 486DX-50. Message-ID: <1992Oct6.110204.1100@sics.se> Date: 6 Oct 92 11:02:04 GMT Sender: news@sics.se Organization: Swedish Institute of Systems Development Lines: 44 I have been running BSD on two different brands of 486-50 boards, and had some strange problems on both of them, which I have tracked down to the external cache memory. They are configured almost identical except that one of them have 64k external cache and the other 256k. They both have: 16 Mbyte memory Adaptec 1542B SCSI controller 1 3 1/2" boot floppy 1.0 Gb Wren7 SCSI disk. I noticed the problems in two ways, one was that when the computer is heavy loaded, random programs started to core dump and the other was that the computers crashed when I was trying to run X386. The first problem was reproduced by forever recompiling the kernel (while 1 ; rm *.o ; make; end), this manifested itself most frequently on the board with 256k cache and very seldom on the 64k cache board. The second problem appeared with a 98% probability on both boards within 5 minutes after starting X. All these problems disappeared when I disabled the external cache. When examining the cave memory chips I found that they were marked that they have 20 ns access time (15 ns for the tag ram) on both of the cards. One of the card manuals stated that this speed should be OK while the other said that the cache memory should have 15/12 ns access time. At the moment I assume that this is the problem, and run with only internal cache. I have filed a complaint at the companies which we have bought the computers from and I am eagerly waiting for the new memory, since it seems to have a 20% effect on performance to run without cache compared to having a 256K cache. Has anyone else encountered problems like this, or am I the only one? Does anyone know how the caches are designed (is it really possible to have the same access time on the cache ram as the clock cycle of the CPU?). Regards Jonas Lagerblad -- Jonas Lagerblad Phone Office: +46-31-830250 Home: +46-31-205955 Car: +46-10-2846031 FAX: +46-31-831047 email: jonas@sisu.se