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From: terry@spcvxb.spc.edu (Terry Kennedy, Operations Mgr.)
Subject: Re: Why one should buy parity memory for reliability?
Nntp-Posting-Host: spcvxa.spc.edu
References: <32485B0D.41C6@austin.ibm.com>
Sender: news@spcuna.spc.edu (Network News)
Organization: St. Peter's College, US
Date: Wed, 25 Sep 1996 21:31:46 GMT
Message-ID: <1996Sep25.173146.1@spcvxb.spc.edu>
Lines: 17
Xref: euryale.cc.adfa.oz.au comp.unix.bsd.freebsd.misc:28010 comp.unix.bsd.bsdi.misc:4988
In article <32485B0D.41C6@austin.ibm.com>, Tushar Patel <tpatel@austin.ibm.com> writes:
> If the Board supports the parity memory and error occurs then in
> theory the OS should be notified and the access should be reapeted.
Unfortunately, the PC's design doesn't latch the failing address, so there
isn't any easy way to determine it. I've seen implementations that scan all
of memory sequentially looking for the error, but there's no guarantee that
the error will happen again.
The ECC designs (like in the Triton II chipset) save the failing address
(and syndrome) which will make it much easier to do so something useful with
the error. However, the upper layers of the OS still need to be modified to
handle de-allocating bad memory, terminating a user process, etc.
Terry Kennedy Operations Manager, Academic Computing
terry@spcvxa.spc.edu St. Peter's College, Jersey City, NJ USA
+1 201 915 9381 (voice) +1 201 435-3662 (FAX)