*BSD News Article 86878


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From: Skipper Smith <skipper@ibmoto.com>
Newsgroups: comp.unix.bsd.freebsd.misc,comp.arch,comp.benchmarks,comp.sys.super
Subject: Re: benchmarking discussion at Usenix?
Date: Thu, 16 Jan 1997 14:45:03 -0500
Organization: IBM/Motorola Somerset Design Center
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Skipper Smith wrote:
[...]
> I don't have any hard numbers, but the industry seems to have decided
> that cache sector sizes equal to 4 or 8 data beats (with the bulk
> choosing 4... 8 is usually an available choice or a side effect) is best
> and that, when organizational purposes require it,  multiple sectors per
> block are acceptable but are generally avoided.  Therefore, you need to
> see your bus width as to what the "line" size should be.

Oh, all of that was applying to on-chip caches.  When going to external
caches, one needs to look very carefully at the kinds of programs that
are expected to run before making any real decisions.  Going with a
generic choice could be a real performance killer in many specific
cases.

-- 
Skipper Smith
Somerset Design Center
All opinions are my own and not those of my employer