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Xref: sserve comp.unix.pc-clone.32bit:770 comp.unix.sysv386:26418 comp.unix.bsd:9109 comp.os.linux:19737 Newsgroups: comp.unix.pc-clone.32bit,comp.unix.sysv386,comp.unix.bsd,comp.os.linux Path: sserve!manuel.anu.edu.au!munnari.oz.au!sgiblab!sdd.hp.com!cs.utexas.edu!news.uta.edu!cse.uta.edu!turbo From: turbo@cse.uta.edu (Chris Turbeville) Subject: Re: ET4000/W32 and VESA VL-Bus Message-ID: <1992Dec17.190542.2662@utagraph.uta.edu> Sender: news@utagraph.uta.edu (USENET News System) Nntp-Posting-Host: cse.uta.edu Organization: Computer Science Engineering at the University of Texas at Arlington References: <BzBEI1.CH@aeon.in-berlin.de> <1992Dec17.080653.4328@Informatik.TU-Muenchen.DE> Date: Thu, 17 Dec 1992 19:05:42 GMT Lines: 25 In article <1992Dec17.080653.4328@Informatik.TU-Muenchen.DE> roell@informatik.tu-muenchen.de (Thomas Roell) writes: .... >a) The performance of a DRAM based accellerator depends VERY much upon > the refresh frequency (i.e. dot-clock). Let's say you have a DRAM > bandwidth of 100MB/sec (let's assume it doesn't matter wether these > are RAS/CAS or RAS/multiple-CAS cycles). If you use a 1024x768 60Hz > resolution, you need about 65MB/sec for screen refresh only. This > leaves you with around 35MB/sec for doing graphics. If you use > 1024x768 72Hz, you need 75MB/sec for screen refresh. That means you > have only 25MB/sec for doing graphics. If you consider that you can > use the fast page mode accesses for screen refresh only and most of > the graphics operation won't be able to use them (since they are > interruped by screen refresh cycles), this computation is in fact > over optimisitic. .... I thought that since EGA boards have been using double ported DRAM to avoid this? Or are you saying 100MBs is for both ports? I have noticed some ads saying their S3 board uses double ported DRAM so are we to assume that most are not? If so then as you say this will instantly destroy any speed a coprocessor can give as the only thing that matters then is faster DRAM. I am no expert (as is obvius to the experts by now) but I am just trying to get this picture. If ram access has always got this refresh overhead (assuming a single port) then any board will simply be limited by DRAM bandwidth. -Chris