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Path: euryale.cc.adfa.oz.au!newshost.carno.net.au!harbinger.cc.monash.edu.au!news.rmit.EDU.AU!news.unimelb.EDU.AU!cs.mu.OZ.AU!munnari.OZ.AU!news.ecn.uoknor.edu!feed1.news.erols.com!news.maxwell.syr.edu!EU.net!Norway.EU.net!uninett.no!not-for-mail From: sthaug@nethelp.no (Steinar Haug) Newsgroups: comp.unix.bsd.freebsd.misc Subject: Re: Am5x86/P75 WB caching... Date: 19 Mar 1997 21:41:13 GMT Organization: Nethelp Consulting, Trondheim, Norway Lines: 22 Message-ID: <5gpmhp$hc7@verdi.nethelp.no> References: <5gnrql$2ut@usenet88.supernews.com> NNTP-Posting-Host: dole.uninett.no In-reply-to: jca@bighorn.accessnv.com's message of 19 Mar 1997 04:59:01 GMT Cache-Post-Path: dole.uninett.no!unknown@verdi.nethelp.no Xref: euryale.cc.adfa.oz.au comp.unix.bsd.freebsd.misc:37389 [J.C. Archambeau] | I just upgraded the CPU in my EISA/VLB motherboard from an i486DX/33 to | an AMD Am5x86/P75 (133). FreeBSD (2.2-BETA) properly indentifies the CPU, | but it states that the L1 cache is in write through mode at bootup. Does | FreeBSD disable write back caching of the Am5x86? If it does, what | define or kernel configuration parameter do I need to change? FreeBSD works fine with writeback. Here's the boot info from a 5x86-133 running in an ASUS PVI-486SP3 motherboard: FreeBSD 2.2-BETA_A #1: Sun Jan 12 15:25:39 MET 1997 sthaug@bizet.nethelp.no:/local/usr/src/sys/compile/GATE Calibrating clock(s) relative to mc146818A clock ... i8254 clock: 1193220 Hz CPU: AMD Am5x86 Write-Back (486-class CPU) Origin = "AuthenticAMD" Id = 0x4f4 real memory = 25165824 (24576K bytes) avail memory = 22835200 (22300K bytes) At least on this motherboard you need to enable writeback with a jumper. Steinar Haug, Nethelp consulting, sthaug@nethelp.no