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Received: by minnie.vk1xwt.ampr.org with NNTP id AA5260 ; Tue, 22 Dec 92 19:00:32 EST Xref: sserve comp.unix.pc-clone.32bit:792 comp.unix.sysv386:26463 comp.unix.bsd:9214 comp.os.linux:19992 Newsgroups: comp.unix.pc-clone.32bit,comp.unix.sysv386,comp.unix.bsd,comp.os.linux Path: sserve!manuel.anu.edu.au!munnari.oz.au!spool.mu.edu!caen!destroyer!cs.ubc.ca!van-bc!bhenning From: bhenning@wimsey.bc.ca (Bill Henning) Subject: Re: ET4000/W32 and VESA VL-Bus Organization: Wimsey Information Services Date: Sun, 20 Dec 1992 20:14:47 GMT Message-ID: <BzKqwn.5vA@wimsey.bc.ca> References: <BzBEI1.CH@aeon.in-berlin.de> <1992Dec20.153314.24148@Informatik.TU-Muenchen.DE> Lines: 10 The problem with DRAM based accelerators, even if they get 160Mb/sec bandwidth out of the DRAM's is that the bandwidth is not random-access, but is rather a result of page mode (or static column, or nibble mode) DRAM cycles, therefore if you are using say 110Mb of bandwidth to feed a 1280x1024x8 display, the theoretically 50Mb/sec bandwitdh left over will actually be more like 10-20Mb/sec, as most graphics operations will not be able to take full advantage of page mode, even if the bus interface to the local bus supports it. Bill