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Path: euryale.cc.adfa.oz.au!newshost.carno.net.au!harbinger.cc.monash.edu.au!munnari.OZ.AU!news.ecn.uoknor.edu!feed1.news.erols.com!howland.erols.net!newsxfer3.itd.umich.edu!news1.best.com!nntp1.ba.best.com!not-for-mail From: dillon@flea.best.net (Matt Dillon) Newsgroups: comp.unix.sco.misc,comp.unix.bsd.freebsd.misc,comp.unix.bsd.bsdi.misc,comp.sys.sgi.misc Subject: Re: no such thing as a "general user community" Date: 25 Mar 1997 16:59:42 -0800 Organization: BEST Internet Communications, Inc. Lines: 33 Message-ID: <5h9sdu$3ag@flea.best.net> References: <331BB7DD.28EC@net5.net> <5glbkq$io6$3@kayrad.ziplink.net> <5gn615$9cu@flea.best.net> <5h92no$gua@innocence.interface-business.de> NNTP-Posting-Host: flea.best.net Xref: euryale.cc.adfa.oz.au comp.unix.sco.misc:37310 comp.unix.bsd.freebsd.misc:37717 comp.unix.bsd.bsdi.misc:6457 comp.sys.sgi.misc:29397 :In article <5h92no$gua@innocence.interface-business.de>, :J Wunsch <joerg_wunsch@interface-business.de> wrote: :>dillon@flea.best.net (Matt Dillon) wrote: :> :>> A disk configuration is a disk configuration no matter what :>> platform you are running on. Memory capacity is memory :>> capacity.. the memory requirements for a particular program are :... :>instructions in order to load a single address, and that all addresses :>are 64-bit there, that you have more wasted space by padding etc. But :>it simply shows that the memory requirements of the same task on an :>Alpha CPU are very likely to be higher than they were on a 32-bit CISC :>CPU. :> :>-- :>J"org Wunsch Unix support engineer :>joerg_wunsch@interface-business.de http://www.interface-business.de/~j Mmm.. respectfully, I would disagree. This might be true for very large binaries, but for most programs the DATA+RSS+ALLOCATION will completely override the size of the TEXT area (portion of the binary that holds the instructions). The only time I see big differences in a ps is with shared libraries, which vary greatly across architectures, but being shared they do not have much impact on the true memory use. I think I *have* noticed differences in L1 and L2 cache effectiveness. RISC boxes tend to need more L1 and L2 cache due to the larger instructions. It's interesting to note that Intel can get away with a measily 256K or 512K L2 cache on its PPROs. For all of its complexity, the x86/386/486/pentium instruction set is pretty compact. -Matt